/* Table of opcodes for the Texas Instruments TMS320C[34]X family.    Copyright (C) 2002-2026 Free Software Foundation, Inc.     Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)      This program is free software; you can redistribute it and/or modify   it under the terms of the GNU General Public License as published by   the Free Software Foundation; either version 3 of the License, or   (at your option) any later version.    This program is distributed in the hope that it will be useful,   but WITHOUT ANY WARRANTY; without even the implied warranty of   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the   GNU General Public License for more details.    You should have received a copy of the GNU General Public License   along with this program; if not, write to the Free Software   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,   MA 02110-1301, USA.  */ #define IS_CPU_TIC3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33)#define IS_CPU_TIC4X(v) ((v) ==  0 || (v) == 40 || (v) == 44) /* Define some bitfield extraction/insertion macros.  */#define EXTRU(inst, m, l) \  (((inst) >> (l)) & ((2u << ((m) - (l))) - 1))#define EXTRS(inst, m, l) \  ((int) ((EXTRU (inst, m, l) ^ (1u << ((m) - (l)))) - (1u << ((m) - (l)))))#define INSERTU(inst, val, m, l) \  ((inst) |= ((val) & ((2u << ((m) - (l))) - 1)) << (l))#define INSERTS INSERTU /* Define register numbers.  */typedef enum  {    REG_R0, REG_R1, REG_R2, REG_R3,    REG_R4, REG_R5, REG_R6, REG_R7,    REG_AR0, REG_AR1, REG_AR2, REG_AR3,    REG_AR4, REG_AR5, REG_AR6, REG_AR7,    REG_DP, REG_IR0, REG_IR1, REG_BK,    REG_SP, REG_ST, REG_DIE, REG_IIE,    REG_IIF, REG_RS, REG_RE, REG_RC,    REG_R8, REG_R9, REG_R10, REG_R11,    REG_IVTP, REG_TVTP  }c4x_reg_t; /* Note that the actual register numbers for IVTP is 0 and TVTP is 1.  */ #define REG_IE REG_DIE		/* C3x only */#define REG_IF REG_IIE		/* C3x only */#define REG_IOF REG_IIF		/* C3x only */ #define TIC3X_REG_MAX REG_RC#define TIC4X_REG_MAX REG_TVTP /* Register table size including C4x expansion regs.  */#define REG_TABLE_SIZE (TIC4X_REG_MAX + 1) struct tic4x_register{  const char *  name;  unsigned long regno;}; typedef struct tic4x_register tic4x_register_t; /* We could store register synonyms here.  */static const tic4x_register_t tic3x_registers[] ={  {"f0",  REG_R0},  {"r0",  REG_R0},  {"f1",  REG_R1},  {"r1",  REG_R1},  {"f2",  REG_R2},  {"r2",  REG_R2},  {"f3",  REG_R3},  {"r3",  REG_R3},  {"f4",  REG_R4},  {"r4",  REG_R4},  {"f5",  REG_R5},  {"r5",  REG_R5},  {"f6",  REG_R6},  {"r6",  REG_R6},  {"f7",  REG_R7},  {"r7",  REG_R7},  {"ar0", REG_AR0},  {"ar1", REG_AR1},  {"ar2", REG_AR2},  {"ar3", REG_AR3},  {"ar4", REG_AR4},  {"ar5", REG_AR5},  {"ar6", REG_AR6},  {"ar7", REG_AR7},  {"dp",  REG_DP},  {"ir0", REG_IR0},  {"ir1", REG_IR1},  {"bk",  REG_BK},  {"sp",  REG_SP},  {"st",  REG_ST},  {"ie",  REG_IE},  {"if",  REG_IF},  {"iof", REG_IOF},  {"rs",  REG_RS},  {"re",  REG_RE},  {"rc",  REG_RC},  {"", 0}}; const unsigned int tic3x_num_registers = (((sizeof tic3x_registers) / (sizeof tic3x_registers[0])) - 1); /* Define C4x registers in addition to C3x registers.  */static const tic4x_register_t tic4x_registers[] ={  {"die", REG_DIE},		/* Clobbers C3x REG_IE */  {"iie", REG_IIE},		/* Clobbers C3x REG_IF */  {"iif", REG_IIF},		/* Clobbers C3x REG_IOF */  {"f8",  REG_R8},  {"r8",  REG_R8},  {"f9",  REG_R9},  {"r9",  REG_R9},  {"f10", REG_R10},  {"r10", REG_R10},  {"f11", REG_R11},  {"r11", REG_R11},  {"ivtp", REG_IVTP},  {"tvtp", REG_TVTP},  {"", 0}}; const unsigned int tic4x_num_registers = (((sizeof tic4x_registers) / (sizeof tic4x_registers[0])) - 1); struct tic4x_cond{  const char *  name;  unsigned long cond;}; typedef struct tic4x_cond tic4x_cond_t; /* Define conditional branch/load suffixes.  Put desired form for   disassembler last.  */static const tic4x_cond_t tic4x_conds[] ={  { "u",    0x00 },  { "c",    0x01 }, { "lo",  0x01 },  { "ls",   0x02 },  { "hi",   0x03 },  { "nc",   0x04 }, { "hs",  0x04 },  { "z",    0x05 }, { "eq",  0x05 },  { "nz",   0x06 }, { "ne",  0x06 },  { "n",    0x07 }, { "l",   0x07 }, { "lt",  0x07 },  { "le",   0x08 },  { "p",    0x09 }, { "gt",  0x09 },  { "nn",   0x0a }, { "ge",  0x0a },  { "nv",   0x0c },  { "v",    0x0d },  { "nuf",  0x0e },  { "uf",   0x0f },  { "nlv",  0x10 },  { "lv",   0x11 },  { "nluf", 0x12 },  { "luf",  0x13 },  { "zuf",  0x14 },  /* Dummy entry, not included in num_conds.  This     lets code examine entry i+1 without checking     if we've run off the end of the table.  */  { "",      0x0}}; const unsigned int tic4x_num_conds = (((sizeof tic4x_conds) / (sizeof tic4x_conds[0])) - 1); struct tic4x_indirect{  const char *  name;  unsigned long modn;}; typedef struct tic4x_indirect tic4x_indirect_t; /* Define indirect addressing modes where:   d displacement (signed)   y ir0   z ir1  */ static const tic4x_indirect_t tic4x_indirects[] ={  { "*+a(d)",   0x00 },  { "*-a(d)",   0x01 },  { "*++a(d)",  0x02 },  { "*--a(d)",  0x03 },  { "*a++(d)",  0x04 },  { "*a--(d)",  0x05 },  { "*a++(d)%", 0x06 },  { "*a--(d)%", 0x07 },  { "*+a(y)",   0x08 },  { "*-a(y)",   0x09 },  { "*++a(y)",  0x0a },  { "*--a(y)",  0x0b },  { "*a++(y)",  0x0c },  { "*a--(y)",  0x0d },  { "*a++(y)%", 0x0e },  { "*a--(y)%", 0x0f },  { "*+a(z)",   0x10 },  { "*-a(z)",   0x11 },  { "*++a(z)",  0x12 },  { "*--a(z)",  0x13 },  { "*a++(z)",  0x14 },  { "*a--(z)",  0x15 },  { "*a++(z)%", 0x16 },  { "*a--(z)%", 0x17 },  { "*a",       0x18 },  { "*a++(y)b", 0x19 },  /* Dummy entry, not included in num_indirects.  This     lets code examine entry i+1 without checking     if we've run off the end of the table.  */  { "",      0x0}}; #define TIC3X_MODN_MAX 0x19 const unsigned int tic4x_num_indirects = (((sizeof tic4x_indirects) / (sizeof tic4x_indirects[0])) - 1); /* Instruction template.  */struct tic4x_inst{  const char *  name;  unsigned long opcode;  unsigned long opmask;  const char *        args;  unsigned long oplevel;}; typedef struct tic4x_inst tic4x_inst_t; /* Opcode infix   B  condition              16--20   U,C,Z,LO,HI, etc.   C  condition              23--27   U,C,Z,LO,HI, etc.    Arguments   ,  required arg follows   ;  optional arg follows    Argument types             bits    [classes] - example   -----------------------------------------------------------   *  indirect (all)          0--15   [A,AB,AU,AF,A2,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - *+AR0(5), *++AR0(IR0)   #  direct (for LDP)        0--15   [Z] - @start, start   @  direct                  0--15   [A,AB,AU,AF,A3,A6,A7,AY,B,BA,BB,BI,B6,B7] - @start, start   A  address register       22--24   [D] - AR0, AR7   B  unsigned integer        0--23   [I,I2] - @start, start  (absolute on C3x, relative on C4x)   C  indirect (disp - C4x)   0--7    [S,SC,S2,T,TC,T2,T2C] - *+AR0(5)   E  register (all)          0--7    [T,TC,T2,T2C] - R0, R7, R11, AR0, DP   e  register (0-11)         0--7    [S,SC,S2] - R0, R7, R11   F  short float immediate   0--15   [AF,B,BA,BB] - 3.5, 0e-3.5e-1   G  register (all)          8--15   [T,TC,T2,T2C] - R0, R7, R11, AR0, DP   g  register (0-11)         0--7    [S,SC,S2] - R0, R7, R11   H  register (0-7)         18--16   [LS,M,P,Q] - R0, R7   I  indirect (no disp)      0--7    [S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)   i  indirect (enhanced)     0--7    [LL,LS,M,P,Q,QC] - *+AR0(1), R5   J  indirect (no disp)      8--15   [LL,LS,P,Q,QC,S,SC,S2,T,TC,T2,T2C] - *+AR0(1), *+AR0(IR0)   j  indirect (enhanced)     8--15   [M] - *+AR0(1), R5   K  register               19--21   [LL,M,Q,QC] - R0, R7   L  register               22--24   [LL,LS,P,Q,QC] - R0, R7   M  register (R2,R3)       22--22   [M] R2, R3   N  register (R0,R1)       23--23   [M] R0, R1   O  indirect(disp - C4x)    8--15   [S,SC,S2,T,TC,T2] - *+AR0(5)   P  displacement (PC Rel)   0--15   [D,J,JS] - @start, start   Q  register (all)          0--15   [A,AB,AU,A2,A3,AY,BA,BI,D,I2,J,JS] - R0, AR0, DP, SP   q  register (0-11)         0--15   [AF,B,BB] - R0, R7, R11   R  register (all)         16--20   [A,AB,AU,AF,A6,A7,R,T,TC] - R0, AR0, DP, SP   r  register (0-11)        16--20   [B,BA,BB,BI,B6,B7,RF,S,SC] - R0, R1, R11   S  short int immediate     0--15   [A,AB,AY,BI] - -5, 5   T  integer (C4x)          16--20   [Z] - -5, 12   U  unsigned integer        0--15   [AU,A3] - 0, 65535   V  vector (C4x: 0--8)      0--4    [Z] - 25, 7   W  short int (C4x)         0--7    [T,TC,T2,T2C] - -3, 5   X  expansion reg (C4x)     0--4    [Z] - IVTP, TVTP   Y  address reg (C4x)      16--20   [Z] - AR0, DP, SP, IR0   Z  expansion reg (C4x)    16--20   [Z] - IVTP, TVTP*/ #define TIC4X_OPERANDS_MAX 7	/* Max number of operands for an inst.  */#define TIC4X_NAME_MAX 16	/* Max number of chars in parallel name.  */ /* Define the instruction level */#define OP_C3X   0x1   /* C30 support - supported by all */#define OP_C4X   0x2   /* C40 support - C40, C44 */#define OP_ENH   0x4   /* Class LL,LS,M,P,Q,QC enhancements. Argument type                          I and J is enhanced in these classes - C31>=6.0,                          C32>=2.0, C33 */#define OP_LPWR  0x8   /* Low power support (LOPOWER, MAXSPEED) - C30>=7.0,                          LC31, C31>=5.0, C32 */#define OP_IDLE2 0x10  /* Idle2 support (IDLE2) - C30>=7.0, LC31, C31>=5.0,                          C32, C33, C40>=5.0, C44 */ /* The following class definition is a classification scheme for   putting instructions with similar type of arguments together. It   simplifies the op-code definitions significantly, as we then only   need to use the class macroes for 95% of the DSP's opcodes.*/ /* A: General 2-operand integer operations   Syntax: <i> src, dst      src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)      dst = Register (R)   Instr: 15/8 - ABSI, ADDC, ADDI, ASH, CMPI, LDI, LSH, MPYI, NEGB, NEGI,                SUBB, SUBC, SUBI, SUBRB, SUBRI, C4x: LBn, LHn, LWLn, LWRn,                MBn, MHn, MPYSHI, MPYUHI*/#define A_CLASS_INSN(name, opcode, level) \  { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \  { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \  { name, opcode|0x00600000, 0xffe00000, "S,R", level } /* AB: General 2-operand integer operation with condition   Syntax: <i>c src, dst       c   = Condition       src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)       dst = Register (R)   Instr: 1/0 - LDIc*/#define AB_CLASS_INSN(name, opcode, level) \  { name, opcode|0x40000000, 0xf0600000, "Q;R", level }, \  { name, opcode|0x40200000, 0xf0600000, "@,R", level }, \  { name, opcode|0x40400000, 0xf0600000, "*,R", level }, \  { name, opcode|0x40600000, 0xf0600000, "S,R", level } /* AU: General 2-operand unsigned integer operation   Syntax: <i> src, dst        src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)        dst = Register (R)   Instr: 6/2 - AND, ANDN, NOT, OR, TSTB, XOR, C4x: LBUn, LHUn*/#define AU_CLASS_INSN(name, opcode, level) \  { name, opcode|0x00000000, 0xffe00000, "Q;R", level }, \  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \  { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \  { name, opcode|0x00600000, 0xffe00000, "U,R", level } /* AF: General 2-operand float to integer operation   Syntax: <i> src, dst        src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)        dst = Register (R)   Instr: 1/0 - FIX*/#define AF_CLASS_INSN(name, opcode, level) \  { name, opcode|0x00000000, 0xffe00000, "q;R", level }, \  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \  { name, opcode|0x00400000, 0xffe00000, "*,R", level }, \  { name, opcode|0x00600000, 0xffe00000, "F,R", level } /* A2: Limited 1-operand (integer) operation   Syntax: <i> src       src = Register (Q), Indirect (*), None   Instr: 1/0 - NOP*/#define A2_CLASS_INSN(name, opcode, level) \  { name, opcode|0x00000000, 0xffe00000, "Q", level }, \  { name, opcode|0x00400000, 0xffe00000, "*", level }, \  { name, opcode|0x00000000, 0xffe00000, "" , level } /* A3: General 1-operand unsigned integer operation   Syntax: <i> src        src = Register (Q), Direct (@), Indirect (*), Unsigned immediate (U)   Instr: 1/0 - RPTS*/#define A3_CLASS_INSN(name, opcode, level) \  { name, opcode|0x00000000, 0xffff0000, "Q", level }, \  { name, opcode|0x00200000, 0xffff0000, "@", level }, \  { name, opcode|0x00400000, 0xffff0000, "*", level }, \  { name, opcode|0x00600000, 0xffff0000, "U", level } /* A6: Limited 2-operand integer operation   Syntax: <i> src, dst       src = Direct (@), Indirect (*)       dst = Register (R)   Instr: 1/1 - LDII, C4x: SIGI*/#define A6_CLASS_INSN(name, opcode, level) \  { name, opcode|0x00200000, 0xffe00000, "@,R", level }, \  { name, opcode|0x00400000, 0xffe00000, "*,R", level } /* A7: Limited 2-operand integer store operation   Syntax: <i> src, dst       src = Register (R)       dst = Direct (@), Indirect (*)   Instr: 2/0 - STI, STII*/#define A7_CLASS_INSN(name, opcode, level) \  { name, opcode|0x00200000, 0xffe00000, "R,@", level }, \  { name, opcode|0x00400000, 0xffe00000, "R,*", level } /* AY: General 2-operand signed address load operation   Syntax: <i> src, dst        src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)        dst = Address register - ARx, IRx, DP, BK, SP (Y)   Instr: 0/1 - C4x: LDA   Note: Q and Y should *never* be the same register*/#define AY_CLASS_INSN(name, opcode, level) \  { name, opcode|0x00000000, 0xffe00000, "Q,Y", level }, \  { name, opcode|0x00200000, 0xffe00000, "@,Y", level }, \  { name, opcode|0x00400000, 0xffe00000, "*,Y", level }, \  { name, opcode|0x00600000, 0xffe00000, "S,Y", level } /* B: General 2-operand float operation   Syntax: <i> src, dst       src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)       dst = Register 0-11 (r)   Instr: 12/2 - ABSF, ADDF, CMPF, LDE, LDF, LDM, MPYF, NEGF, NORM, RND,                 SUBF, SUBRF, C4x: RSQRF, TOIEEE*/#define B_CLASS_INSN(name, opcode, level) \  { name, opcode|0x00000000, 0xffe00000, "q;r", level }, \  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \  { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \  { name, opcode|0x00600000, 0xffe00000, "F,r", level } /* BA: General 2-operand integer to float operation   Syntax: <i> src, dst       src = Register (Q), Direct (@), Indirect (*), Float immediate (F)       dst = Register 0-11 (r)   Instr: 0/1 - C4x: CRCPF*/#define BA_CLASS_INSN(name, opcode, level) \  { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \  { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \  { name, opcode|0x00600000, 0xffe00000, "F,r", level } /* BB: General 2-operand conditional float operation   Syntax: <i>c src, dst       c   = Condition       src = Register 0-11 (q), Direct (@), Indirect (*), Float immediate (F)       dst = Register 0-11 (r)   Instr: 1/0 - LDFc*/#define BB_CLASS_INSN(name, opcode, level) \  { name, opcode|0x40000000, 0xf0600000, "q;r", level }, \  { name, opcode|0x40200000, 0xf0600000, "@,r", level }, \  { name, opcode|0x40400000, 0xf0600000, "*,r", level }, \  { name, opcode|0x40600000, 0xf0600000, "F,r", level } /* BI: General 2-operand integer to float operation (yet different to BA)   Syntax: <i> src, dst       src = Register (Q), Direct (@), Indirect (*), Signed immediate (S)       dst = Register 0-11 (r)   Instr: 1/0 - FLOAT*/#define BI_CLASS_INSN(name, opcode, level) \  { name, opcode|0x00000000, 0xffe00000, "Q;r", level }, \  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \  { name, opcode|0x00400000, 0xffe00000, "*,r", level }, \  { name, opcode|0x00600000, 0xffe00000, "S,r", level } /* B6: Limited 2-operand float operation    Syntax: <i> src, dst       src = Direct (@), Indirect (*)       dst = Register 0-11 (r)   Instr: 1/1 - LDFI, C4x: FRIEEE*/#define B6_CLASS_INSN(name, opcode, level) \  { name, opcode|0x00200000, 0xffe00000, "@,r", level }, \  { name, opcode|0x00400000, 0xffe00000, "*,r", level } /* B7: Limited 2-operand float store operation   Syntax: <i> src, dst       src = Register 0-11 (r)       dst = Direct (@), Indirect (*)   Instr: 2/0 - STF, STFI*/#define B7_CLASS_INSN(name, opcode, level) \  { name, opcode|0x00200000, 0xffe00000, "r,@", level }, \  { name, opcode|0x00400000, 0xffe00000, "r,*", level } /* D: Decrement and brach operations   Syntax: <i>c ARn, dst       c   = condition       ARn = AR register 0-7 (A)       dst = Register (Q), PC-relative (P)   Instr: 2/0 - DBc, DBcD   Alias: <name1> <name2>*/#define D_CLASS_INSN(name1, name2, opcode, level) \  { name1, opcode|0x00000000, 0xfe200000, "A,Q", level }, \  { name1, opcode|0x02000000, 0xfe200000, "A,P", level }, \  { name2, opcode|0x00000000, 0xfe200000, "A,Q", level }, \  { name2, opcode|0x02000000, 0xfe200000, "A,P", level } /* I: General branch operations   Syntax: <i> dst       dst = Address (B)   Instr: 3/1 - BR, BRD, CALL, C4x: LAJ*/ /* I2: General branch operations (C4x addition)   Syntax: <i> dst       dst = Address (B), C4x: Register (Q)

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