/* Opcode table for the H8/300   Copyright (C) 1991-2026 Free Software Foundation, Inc.   Written by Steve Chamberlain <sac@cygnus.com>.      This file is part of GDB, the GNU Debugger and GAS, the GNU Assembler.      This program is free software; you can redistribute it and/or modify   it under the terms of the GNU General Public License as published by   the Free Software Foundation; either version 3 of the License, or   (at your option) any later version.      This program is distributed in the hope that it will be useful,   but WITHOUT ANY WARRANTY; without even the implied warranty of   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the   GNU General Public License for more details.      You should have received a copy of the GNU General Public License   along with this program; if not, write to the Free Software   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA   02110-1301, USA.  */ /* Instructions are stored as a sequence of nibbles.   If the nibble has value 15 or less than the representation is complete.   Otherwise, we record what it contains with several flags.  */ typedef int op_type; enum h8_flags{  L_2  =	0x10,  L_3  =	0x20,  /* 3 bit constant, zero not accepted.  */  L_3NZ =	0x30,  L_4  =	0x40,  L_5  =	0x50,  L_8  =	0x60,  L_8U =	0x70,  L_16 =	0x80,  L_16U =	0x90,  L_24 =	0xA0,  L_32 =	0xB0,  L_P  =	0xC0,   /* Mask to isolate the L_x size bits.  */  SIZE =	0xF0,   REG =		0x0100,  ABS =		0x0200,  MEMIND =	0x0300,  IMM =		0x0400,  DISP =	0x0500,  IND =		0x0600,  POSTINC =	0x0700,  POSTDEC =	0x0800,  PREINC =	0x0900,  PREDEC =	0x0A00,  PCREL =	0x0B00,  KBIT =	0x0C00,  DBIT =	0x0D00,  CONST_2 =     0x0E00,  CONST_4 =     0x0F00,  CONST_8 =     0x1000,  CONST_16 =    0x1100,  INDEXB =      0x1200,  INDEXW =      0x1300,  INDEXL =      0x1400,  PCIDXB =      0x1500,  PCIDXW =      0x1600,  PCIDXL =      0x1700,  VECIND =      0x1800,  LOWREG =      0x1900,  DATA   =      0x2000,   /* Synonyms.  */  INC =		POSTINC,  DEC =		PREDEC,  /* Control Registers.  */  CCR =		0x4000,  EXR =		0x4100,  MACH = 	0x4200,  MACL = 	0x4300,  RESERV1 = 	0x4400,  RESERV2 = 	0x4500,  VBR = 	0x4600,  SBR = 	0x4700,  MACREG =	0x4800,  CCR_EXR = 	0x4900,  VBR_SBR = 	0x4A00,  CC_EX_VB_SB =	0x4B00,  RESERV3 =	0x4C00,  RESERV4 = 	0x4D00,  RESERV5 = 	0x4E00,  RESERV6 = 	0x4F00,   /* Mask to isolate the addressing mode bits (REG .. PREDEC).  */  MODE =	0x7F00,   CTRL = 	0x4000,   NO_SYMBOLS =  0x8000,  SRC =		0x10000,  DST =		0x20000,  OP3 =		0x40000,  MEMRELAX = 	0x80000,		/* Move insn which may relax.  */   DISPREG =	0x100000,  IGNORE =	0x200000,  ABSJMP =	0x400000,   B00 =         0x800000, 		/* Bit 0 must be low.   */  B01 =         0x1000000, 		/* Bit 0 must be high.  */  B10 = 	0x2000000, 		/* Bit 1 must be low.   */  B11 = 	0x4000000, 		/* Bit 1 must be high.  */  B20 = 	0x8000000, 		/* Bit 2 must be low.   */  B21 = 	0x10000000, 		/* Bit 2 must be high.  */  B30 =		0x20000000, 		/* Bit 3 must be low.   */  B31 =		0x40000000,		/* Bit 3 must be high.  */  E =  		0x80000000,		/* End of nibble sequence.  */   /* Immediates smaller than 8 bits are always unsigned.  */  IMM3 =	IMM | L_3,  IMM4 =	IMM | L_4,  IMM5 =	IMM | L_5,  IMM3NZ =	IMM | L_3NZ,  IMM2 =	IMM | L_2,   IMM8 =	IMM | SRC | L_8,  IMM8U =	IMM | SRC | L_8U,  IMM16 =	IMM | SRC | L_16,  IMM16U =	IMM | SRC | L_16U,  IMM32 =	IMM | SRC | L_32,   IMM3NZ_NS =   IMM3NZ | NO_SYMBOLS,  IMM4_NS =	IMM4 | NO_SYMBOLS,  IMM8U_NS =	IMM8U | NO_SYMBOLS,  IMM16U_NS =   IMM16U | NO_SYMBOLS,   RD8  =	DST | L_8  | REG,  RD16 =	DST | L_16 | REG,  RD32 =	DST | L_32 | REG,  R3_8  =       OP3 | L_8  | REG,  R3_16 =       OP3 | L_16 | REG,  R3_32 =       OP3 | L_32 | REG,  RS8  =	SRC | L_8  | REG,  RS16 =	SRC | L_16 | REG,  RS32 =	SRC | L_32 | REG,   RSP =		SRC | L_P | REG,  RDP =		DST | L_P | REG,   PCREL8 =	PCREL | L_8,  PCREL16 =	PCREL | L_16,   OP3PCREL8 =	OP3 | PCREL | L_8,  OP3PCREL16 =	OP3 | PCREL | L_16,   INDEXB16  =	INDEXB | L_16,  INDEXW16  =	INDEXW | L_16,  INDEXL16  =	INDEXL | L_16,  INDEXB16D =	INDEXB | L_16 | DST,  INDEXW16D =	INDEXW | L_16 | DST,  INDEXL16D =	INDEXL | L_16 | DST,   INDEXB32  =	INDEXB | L_32,  INDEXW32  =	INDEXW | L_32,  INDEXL32  =	INDEXL | L_32,  INDEXB32D =	INDEXB | L_32 | DST,  INDEXW32D =	INDEXW | L_32 | DST,  INDEXL32D =	INDEXL | L_32 | DST,   DISP2SRC =	DISP | L_2  | SRC,  DISP16SRC =	DISP | L_16 | SRC,  DISP32SRC =	DISP | L_32 | SRC,   DISP2DST =	DISP | L_2  | DST,  DISP16DST =	DISP | L_16 | DST,  DISP32DST =	DISP | L_32 | DST,   DSTDISPREG =  DST | DISPREG,  SRCDISPREG =  SRC | DISPREG,   ABS8SRC  = 	SRC | ABS | L_8,  ABS16SRC = 	SRC | ABS | L_16U,  ABS24SRC = 	SRC | ABS | L_24,  ABS32SRC = 	SRC | ABS | L_32,   ABS8DST  =	DST | ABS | L_8,  ABS16DST = 	DST | ABS | L_16U,  ABS24DST = 	DST | ABS | L_24,  ABS32DST = 	DST | ABS | L_32,   ABS8OP3  =	OP3 | ABS | L_8,  ABS16OP3 = 	OP3 | ABS | L_16U,  ABS24OP3 = 	OP3 | ABS | L_24,  ABS32OP3 = 	OP3 | ABS | L_32,   RDDEC =	DST | DEC,  RSINC =	SRC | INC,  RDINC =	DST | INC,   RSPOSTINC =	SRC | POSTINC,  RDPOSTINC =	DST | POSTINC,  RSPREINC =	SRC | PREINC,  RDPREINC =	DST | PREINC,  RSPOSTDEC =	SRC | POSTDEC,  RDPOSTDEC =	DST | POSTDEC,  RSPREDEC =	SRC | PREDEC,  RDPREDEC =	DST | PREDEC,   RSIND =	SRC | IND,  RDIND =	DST | IND,  R3_IND = 	OP3 | IND, #define MS32	(SRC | L_32 | MACREG)#define MD32	(DST | L_32 | MACREG) #if 1  OR8  =	RS8,		/* ??? OR as in One Register.  */  OR16 =	RS16,  OR32 =	RS32,#else  OR8  =	RD8,  OR16 =	RD16,  OR32 =	RD32#endif}; enum ctrlreg{  C_CCR  = 0,   C_EXR  = 1,   C_MACH = 2,   C_MACL = 3,   C_VBR  = 6,   C_SBR  = 7}; enum {MAX_CODE_NIBBLES = 33}; struct code {  op_type nib[MAX_CODE_NIBBLES];}; struct arg {  op_type nib[3];}; /* Availability of instructions on processor models.  */enum h8_model{  AV_H8,  AV_H8H,  AV_H8S,  AV_H8SX}; struct h8_opcode {  int how;  enum h8_model available;  int time;  const char *name;  struct arg args;  struct code data;}; #ifdef DEFINE_TABLE #define DATA2   DATA, DATA#define DATA3   DATA, DATA, DATA#define DATA5   DATA, DATA, DATA, DATA, DATA#define DATA7   DATA, DATA, DATA, DATA, DATA, DATA, DATA #define IMM8LIST	IMM8,   DATA#define IMM16LIST	IMM16,  DATA3#define IMM16ULIST	IMM16U, DATA3#define IMM24LIST	IMM24,  DATA5#define IMM32LIST	IMM32,  DATA7 #define DISP16LIST DISP | L_16, DATA3#define DISP24LIST DISP | L_24, DATA5#define DISP32LIST DISP | L_32, DATA7 #define ABS8LIST   ABS  | L_8,   DATA#define ABS16LIST  ABS  | L_16U, DATA3#define ABS24LIST  ABS  | L_24,  DATA5#define ABS32LIST  ABS  | L_32,  DATA7 #define DSTABS8LIST  DST | ABS | L_8,   DATA#define DSTABS16LIST DST | ABS | L_16U, DATA3#define DSTABS24LIST DST | ABS | L_24,  DATA5#define DSTABS32LIST DST | ABS | L_32,  DATA7 #define OP3ABS8LIST  OP3 | ABS | L_8,  DATA#define OP3ABS16LIST OP3 | ABS | L_16, DATA3#define OP3ABS24LIST OP3 | ABS | L_24, DATA5#define OP3ABS32LIST OP3 | ABS | L_32, DATA7 #define DSTDISP16LIST DST | DISP | L_16, DATA3#define DSTDISP24LIST DST | DISP | L_24, DATA5#define DSTDISP32LIST DST | DISP | L_32, DATA7 #define A16LIST   L_16,  DATA3#define A24LIST   L_24,  DATA5#define A32LIST   L_32,  DATA7 /* Extended Operand Prefixes:  */ #define PREFIX_010	0x0, 0x1, 0x0#define PREFIX_015	0x0, 0x1, 0x5#define PREFIX_017	0x0, 0x1, 0x7 #define PREFIX_0100	0x0, 0x1, 0x0, 0x0#define PREFIX_010_D2	0x0, 0x1, 0x0, B30 | B21 | DISP2SRC#define PREFIX_0101	0x0, 0x1, 0x0, 0x1#define PREFIX_0102	0x0, 0x1, 0x0, 0x2#define PREFIX_0103	0x0, 0x1, 0x0, 0x3#define PREFIX_0104	0x0, 0x1, 0x0, 0x4#define PREFIX_0105	0x0, 0x1, 0x0, 0x5#define PREFIX_0106	0x0, 0x1, 0x0, 0x6#define PREFIX_0107	0x0, 0x1, 0x0, 0x7#define PREFIX_0108	0x0, 0x1, 0x0, 0x8#define PREFIX_0109	0x0, 0x1, 0x0, 0x9#define PREFIX_010A	0x0, 0x1, 0x0, 0xa#define PREFIX_010D	0x0, 0x1, 0x0, 0xd#define PREFIX_010E	0x0, 0x1, 0x0, 0xe #define PREFIX_0150	0x0, 0x1, 0x5, 0x0#define PREFIX_015_D2	0x0, 0x1, 0x5, B30 | B21 | DISP2SRC#define PREFIX_0151	0x0, 0x1, 0x5, 0x1#define PREFIX_0152	0x0, 0x1, 0x5, 0x2#define PREFIX_0153	0x0, 0x1, 0x5, 0x3#define PREFIX_0154	0x0, 0x1, 0x5, 0x4#define PREFIX_0155	0x0, 0x1, 0x5, 0x5#define PREFIX_0156	0x0, 0x1, 0x5, 0x6#define PREFIX_0157	0x0, 0x1, 0x5, 0x7#define PREFIX_0158	0x0, 0x1, 0x5, 0x8#define PREFIX_0159	0x0, 0x1, 0x5, 0x9#define PREFIX_015A	0x0, 0x1, 0x5, 0xa#define PREFIX_015D	0x0, 0x1, 0x5, 0xd#define PREFIX_015E	0x0, 0x1, 0x5, 0xe#define PREFIX_015F	0x0, 0x1, 0x5, 0xf #define PREFIX_0170	0x0, 0x1, 0x7, 0x0#define PREFIX_017_D2S	0x0, 0x1, 0x7, B30 | B21 | DISP2SRC#define PREFIX_017_D2D	0x0, 0x1, 0x7, B30 | B21 | DISP2DST#define PREFIX_0171	0x0, 0x1, 0x7, 0x1#define PREFIX_0172	0x0, 0x1, 0x7, 0x2#define PREFIX_0173	0x0, 0x1, 0x7, 0x3#define PREFIX_0174	0x0, 0x1, 0x7, 0x4#define PREFIX_0175	0x0, 0x1, 0x7, 0x5#define PREFIX_0176	0x0, 0x1, 0x7, 0x6#define PREFIX_0177	0x0, 0x1, 0x7, 0x7#define PREFIX_0178	0x0, 0x1, 0x7, 0x8#define PREFIX_0179	0x0, 0x1, 0x7, 0x9#define PREFIX_017A	0x0, 0x1, 0x7, 0xa#define PREFIX_017D	0x0, 0x1, 0x7, 0xd#define PREFIX_017E	0x0, 0x1, 0x7, 0xe#define PREFIX_017F	0x0, 0x1, 0x7, 0xf #define PREFIX_6A15	0x6, 0xa, 0x1, 0x5#define PREFIX_6A35	0x6, 0xa, 0x3, 0x5#define PREFIX_6B15	0x6, 0xb, 0x1, 0x5#define PREFIX_6B35	0x6, 0xb, 0x3, 0x5 #define PREFIX_78R4	0x7, 0x8, B31 | DISPREG, 0x4#define PREFIX_78R5	0x7, 0x8, B31 | DISPREG, 0x5#define PREFIX_78R6	0x7, 0x8, B31 | DISPREG, 0x6#define PREFIX_78R7	0x7, 0x8, B31 | DISPREG, 0x7 #define PREFIX_78R4W	0x7, 0x8, B30 | DISPREG, 0x4#define PREFIX_78R5W	0x7, 0x8, B30 | DISPREG, 0x5#define PREFIX_78R6W	0x7, 0x8, B30 | DISPREG, 0x6#define PREFIX_78R7W	0x7, 0x8, B30 | DISPREG, 0x7 #define PREFIX_78R4WD	0x7, 0x8, B30 | DSTDISPREG, 0x4#define PREFIX_78R5WD	0x7, 0x8, B30 | DSTDISPREG, 0x5#define PREFIX_78R6WD	0x7, 0x8, B30 | DSTDISPREG, 0x6#define PREFIX_78R7WD	0x7, 0x8, B30 | DSTDISPREG, 0x7 #define PREFIX_7974	0x7, 0x9, 0x7, 0x4#define PREFIX_7A74	0x7, 0xa, 0x7, 0x4#define PREFIX_7A7C	0x7, 0xa, 0x7, 0xc  /* Source standard fragment:  */#define FROM_IND	 0, RSIND#define FROM_POSTINC	 8, RSPOSTINC#define FROM_POSTDEC	10, RSPOSTDEC#define FROM_PREINC	 9, RSPREINC#define FROM_PREDEC	11, RSPREDEC#define FROM_DISP2	B30 | B20 | DISP2SRC, DISPREG #define FROM_DISP16	12, B30 | DISPREG#define FROM_DISP32	12, B31 | DISPREG#define FROM_DISP16B	13, B30 | DISPREG#define FROM_DISP16W	14, B30 | DISPREG#define FROM_DISP16L	15, B30 | DISPREG#define FROM_DISP32B	13, B31 | DISPREG#define FROM_DISP32W	14, B31 | DISPREG#define FROM_DISP32L	15, B31 | DISPREG#define FROM_ABS16	 4, B30 | IGNORE#define FROM_ABS32	 4, B31 | IGNORE /* Destination standard fragment:  */#define TO_IND		 0, RDIND#define TO_IND_MOV	 0, RDIND | B30#define TO_POSTINC	 8, RDPOSTINC#define TO_POSTINC_MOV	 8, RDPOSTINC | B30#define TO_POSTDEC	10, RDPOSTDEC#define TO_POSTDEC_MOV	10, RDPOSTDEC | B30#define TO_PREINC	 9, RDPREINC#define TO_PREINC_MOV	 9, RDPREINC  | B30#define TO_PREDEC	11, RDPREDEC#define TO_PREDEC_MOV	11, RDPREDEC  | B30#define TO_DISP2	B30 | B20 | DISP2DST, DSTDISPREG#define TO_DISP2_MOV	B30 | B20 | DISP2DST, DSTDISPREG | B30#define TO_DISP16	12, B30 | DSTDISPREG#define TO_DISP32	12, B31 | DSTDISPREG#define TO_DISP16B	13, B30 | DSTDISPREG#define TO_DISP16W	14, B30 | DSTDISPREG#define TO_DISP16L	15, B30 | DSTDISPREG#define TO_DISP32B	13, B31 | DSTDISPREG#define TO_DISP32W	14, B31 | DSTDISPREG#define TO_DISP32L	15, B31 | DSTDISPREG#define TO_ABS16	 4, B30 | IGNORE#define TO_ABS32	 4, B31 | IGNORE /* Source fragment for three-word instruction:  */#define TFROM_IND	6,  9, B30 | RSIND, 12#define TFROM_DISP2	6,  9, B30 | DISPREG, 12#define TFROM_ABS16	6, 11, B30 | B20 | B10 | IGNORE, 12, ABS16LIST#define TFROM_ABS32	6, 11, B30 | B20 | B11 | IGNORE, 12, ABS32LIST#define TFROM_POSTINC	6, 13, B30 | RSPOSTINC, 12#define TFROM_PREINC	6, 13, B30 | RSPREINC, 12#define TFROM_POSTDEC	6, 13, B30 | RSPOSTDEC, 12#define TFROM_PREDEC	6, 13, B30 | RSPREDEC, 12#define TFROM_DISP16	6, 15, B30 | DISPREG, 12, DISP16LIST#define TFROM_DISP32	6, 11, 2, 12, DISP32LIST#define TFROM_DISP16B	6, 15, B30 | DISPREG, 12, DISP16LIST#define TFROM_DISP16W	6, 15, B30 | DISPREG, 12, DISP16LIST#define TFROM_DISP16L	6, 15, B30 | DISPREG, 12, DISP16LIST#define TFROM_DISP32B	6, 11, 2, 12, DISP32LIST#define TFROM_DISP32W	6, 11, 2, 12, DISP32LIST#define TFROM_DISP32L	6, 11, 2, 12, DISP32LIST#define TFROM_ABS16W	6, 11, 1, 12, ABS16LIST#define TFROM_ABS32W	6, 11, 3, 12, ABS32LIST /* Source fragment for three-word instruction:  */#define TFROM_IND_B	6,  8, B30 | RSIND, 12#define TFROM_ABS16_B	6, 10, B30 | B20 | B10 | IGNORE, 12, ABS16LIST#define TFROM_ABS32_B	6, 10, B30 | B20 | B11 | IGNORE, 12, ABS32LIST #define TFROM_DISP2_B	6,  8, B30 | DISPREG, 12#define TFROM_POSTINC_B	6, 12, B30 | RSPOSTINC, 12#define TFROM_PREINC_B	6, 12, B30 | RSPREINC, 12#define TFROM_POSTDEC_B	6, 12, B30 | RSPOSTDEC, 12#define TFROM_PREDEC_B	6, 12, B30 | RSPREDEC, 12#define TFROM_DISP16_B	6, 14, B30 | DISPREG, 12, DISP16LIST#define TFROM_DISP32_B	6, 10, 2, 12, DISP32LIST#define TFROM_DISP16B_B	6, 14, B30 | DISPREG, 12, DISP16LIST#define TFROM_DISP16W_B	6, 14, B30 | DISPREG, 12, DISP16LIST#define TFROM_DISP16L_B	6, 14, B30 | DISPREG, 12, DISP16LIST#define TFROM_DISP32B_B	6, 10, 2, 12, DISP32LIST#define TFROM_DISP32W_B	6, 10, 2, 12, DISP32LIST#define TFROM_DISP32L_B	6, 10, 2, 12, DISP32LIST #define TFROM_ABS16W_B	6, 10, 1, 12, ABS16LIST#define TFROM_ABS32W_B	6, 10, 3, 12, ABS32LIST /* Extended Operand Class Expanders:  */ #define MOVFROM_STD(CODE, PREFIX, NAME, SRC, SRC_INFIX) \  {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}},  {{PREFIX, SRC_INFIX, TO_IND_MOV,     E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}},  {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}},  {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}},  {{PREFIX, SRC_INFIX, TO_PREINC_MOV,  E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}},  {{PREFIX, SRC_INFIX, TO_PREDEC_MOV,  E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}},  {{PREFIX, SRC_INFIX, TO_DISP2_MOV,   E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP16,  DSTDISP16LIST, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP32,  DSTDISP32LIST, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16B, DSTDISP16LIST, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16W, DSTDISP16LIST, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL16D, E}},  {{PREFIX, SRC_INFIX, TO_DISP16L, DSTDISP16LIST, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32B, DSTDISP32LIST, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXW32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32W, DSTDISP32LIST, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXL32D, E}},  {{PREFIX, SRC_INFIX, TO_DISP32L, DSTDISP32LIST, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS16DST,  E}},  {{PREFIX, SRC_INFIX, TO_ABS16,   DSTABS16LIST,  E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, ABS32DST,  E}},  {{PREFIX, SRC_INFIX, TO_ABS32,   DSTABS32LIST,  E}}} #define MOVFROM_AD(CODE, PREFIX, NAME, SRC, SRC_INFIX, SRC_SUFFIX) \  {CODE, AV_H8SX, 0, NAME, {{SRC, RDIND,     E}},  {{PREFIX, SRC_INFIX, TO_IND_MOV,     SRC_SUFFIX, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}},  {{PREFIX, SRC_INFIX, TO_POSTINC_MOV, SRC_SUFFIX, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}},  {{PREFIX, SRC_INFIX, TO_POSTDEC_MOV, SRC_SUFFIX, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC,  E}},  {{PREFIX, SRC_INFIX, TO_PREINC_MOV,  SRC_SUFFIX, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC,  E}},  {{PREFIX, SRC_INFIX, TO_PREDEC_MOV,  SRC_SUFFIX, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST,  E}},  {{PREFIX, SRC_INFIX, TO_DISP2_MOV,   SRC_SUFFIX, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP16,  SRC_SUFFIX, DSTDISP16LIST, E}}}, \  {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}},  {{PREFIX, SRC_INFIX, TO_DISP32,  SRC_SUFFIX, DSTDISP32LIST, E}}}, \

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